1 -- title: I2S I/F
2 -- author: Sebastian Weiss
3 -- last change: 23.10.13
4
5
6 library IEEE;
7 use IEEE.std_logic_1164.all;
8 use IEEE.numeric_std.all;
9 use IEEE.math_real.all;
10
11 entity i2s is
12 generic
13 (
14 prescaler : natural := 2
15 );
16
17 port
18 (
19 mck : in std_logic;
20 dclk : out std_logic;
21 sd : out std_logic;
22 ws : out std_logic;
23 ch0 : in std_logic_vector(15 downto 0);
24 ch1 : in std_logic_vector(15 downto 0)
25 );
26 end entity;
27
28 architecture behavioral of i2s is
29 constant log2pre : integer := integer(ceil(log2(real(prescaler))));
30 signal pre : unsigned(log2pre-1 downto 0) := (others => '0');
31 signal wsd : std_logic := '0';
32 signal wsdd : std_logic := '0';
33 signal wsp : std_logic := '0';
34 signal sr : std_logic_vector(15 downto 0);
35 signal cnt : unsigned(7 downto 0) := (others => '0');
36 signal wsi : std_logic := '0';
37 signal dclki : std_logic := '0';
38 signal clk_en : std_logic := '0';
39 begin
40
41 process begin
42 wait until rising_edge(mck);
43 pre <= pre + 1;
44 if pre = 0 then
45 clk_en <= '1';
46 else
47 clk_en <= '0';
48 end if;
49 end process;
50
51 process begin
52 wait until rising_edge(mck);
53 if clk_en = '1' then
54 cnt <= cnt + 1;
55 end if;
56 end process;
57
58 dclki <= cnt(2);
59 wsi <= cnt(7);
60
61 process begin
62 wait until rising_edge(dclki);
63 wsd <= wsi;
64 wsdd <= wsd;
65 wsp <= wsd xor wsdd;
66 end process;
67
68 process begin
69 wait until falling_edge(dclki);
70 if wsp = '1' then
71 if wsd = '1' then
72 sr <= ch1;
73 else
74 sr <= ch0;
75 end if;
76 else
77 sr(0) <= '0';
78 sr(15 downto 1) <= sr(14 downto 0);
79 end if;
80 end process;
81
82 sd <= sr(15);
83 ws <= wsd;
84 dclk <= dclki;
85
86 end behavioral;
87
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