1 -- title: CIC
2 -- author: Sebastian Weiss
3 -- last change: 10.10.13
4
5
6 library IEEE;
7 use IEEE.std_logic_1164.all;
8 use IEEE.numeric_std.all;
9 use IEEE.math_real.all;
10
11 entity cic is
12 generic
13 (
14 R : natural := 4; -- decimation factor
15 N : natural := 4; -- number of stages
16 W : natural := 8 -- data width
17 );
18
19 port
20 (
21 clk : in std_logic; -- clock
22 d : in signed(W-1 downto 0); -- data input
23 q : out signed(W-1+N*integer(ceil(log2(real(R)))) downto 0); -- data output
24 rdy : out std_logic -- new output sample ready
25 );
26 end entity;
27
28 architecture behavioral of cic is
29 constant log2R : integer := integer(ceil(log2(real(R))));
30 constant growth : integer := N*log2R;
31 type signed_vector is array(natural range <>) of signed(W-1+growth downto 0);
32 type signed_matrix is array(natural range <>) of signed_vector(N downto 0);
33 signal clkdiv : signed(log2R-1 downto 0) := (others => '0');
34 signal clken : std_logic;
35 signal int : signed_vector(N downto 0) := ((others=> (others=>'0'))); -- integrator stages
36 signal com : signed_matrix(1 downto 0) := ((others=> (others=> (others=>'0')))); -- comb stages
37 begin
38
39 process begin
40 wait until rising_edge(clk);
41 clkdiv <= clkdiv + 1;
42 if clkdiv = 0 then
43 clken <= '1';
44 else
45 clken <= '0';
46 end if;
47 end process;
48
49 process begin
50 wait until rising_edge(clk);
51 int(0) <= resize(d,W+growth);
52 for i in 1 to N loop
53 int(i) <= int(i) + int(i-1);
54 end loop;
55 end process;
56
57 process begin
58 wait until rising_edge(clk);
59 if clken = '1' then
60 com(0)(0) <= int(N);
61 for j in 0 to N-1 loop
62 com(1)(j) <= com(0)(j);
63 end loop;
64 for j in 1 to N loop
65 com(0)(j) <= com(0)(j-1) - com(1)(j-1);
66 end loop;
67 end if;
68 rdy <= clken;
69 end process;
70
71 q <= com(0)(N);
72
73 end behavioral;
74
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