1 -- title: I/Q Mixer
2 -- author: Sebastian Weiss
3 -- last change: 22.10.13
4
5 library IEEE;
6 use IEEE.std_logic_1164.all;
7 use IEEE.numeric_std.all;
8
9 entity iqmix is
10 generic
11 (
12 NCO_A : natural := 16; -- amplitude resolution
13 NCO_F : natural := 24; -- frequency resolution
14 NCO_P : natural := 24; -- phase resolution
15 NCO_N : natural := 14; -- number of stages in nco
16 CIC_R : natural := 256; -- decimation factor
17 CIC_N : natural := 5; -- number of stages in CIC
18 CIC_W : natural := 16 -- CIC width
19 );
20
21 port
22 (
23 clk : in std_logic;
24 fcw : in unsigned(NCO_F-1 downto 0);
25
26 rf : in signed(7 downto 0);
27 i : out signed(15 downto 0);
28 q : out signed(15 downto 0);
29 rdy : out std_logic
30 );
31 end entity;
32
33 architecture behavioral of iqmix is
34 signal mul_i : signed(23 downto 0) := (others => '0');
35 signal mul_q : signed(23 downto 0) := (others => '0');
36 signal nco_i : signed(15 downto 0);
37 signal nco_q : signed(15 downto 0);
38 signal cic_i_d : signed(15 downto 0) := (others => '0');
39 signal cic_q_d : signed(15 downto 0) := (others => '0');
40 signal cic_i_q : signed(15 downto 0);
41 signal cic_q_q : signed(15 downto 0);
42 begin
43
44 cic_i : entity work.cic
45 generic map(
46 R => CIC_R,
47 N => CIC_N,
48 W => CIC_W
49 )
50
51 port map(
52 clk => clk,
53 d => cic_i_d,
54 q => cic_i_q,
55 rdy => rdy
56 );
57
58 cic_q : entity work.cic
59 generic map(
60 R => CIC_R,
61 N => CIC_N,
62 W => CIC_W
63 )
64
65 port map(
66 clk => clk,
67 d => cic_q_d,
68 q => cic_q_q,
69 rdy => open
70 );
71
72 nco : entity work.nco
73 generic map(
74 A => NCO_A,
75 P => NCO_P,
76 F => NCO_F,
77 N => NCO_N
78 )
79
80 port map(
81 clk => clk,
82 fcw => fcw,
83 sin => nco_i,
84 cos => nco_q
85 );
86
87 process
88 begin
89 wait until rising_edge(clk);
90 mul_i <= rf * nco_i;
91 mul_q <= rf * nco_q;
92 end process;
93
94
95 cic_i_d <= mul_i(23 downto 8);
96 cic_q_d <= mul_q(23 downto 8);
97
98 i <= cic_i_q;
99 q <= cic_q_q;
100
101 end behavioral;
102
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