1 -- title: CORDIC
2 -- author: Sebastian Weiss
3 -- last change: 22.10.13
4
5 library IEEE;
6 use IEEE.std_logic_1164.all;
7 use IEEE.numeric_std.all;
8 use IEEE.math_real.all;
9
10 entity cordic is
11 generic
12 (
13 A : natural := 16; -- amplitude resolution
14 P : natural := 24; -- phase resolution
15 N : natural := 14 -- number of stages
16 );
17
18 port
19 (
20 clk : in std_logic; -- signal processing clock
21 phi : in unsigned(P-3 downto 0); -- phase input (0° - 90°)
22 sin : out signed(A-1 downto 0); -- sine output
23 cos : out signed(A-1 downto 0) -- cosine output
24 );
25 end entity;
26
27 architecture behavioral of cordic is
28 type alpha_t is array(0 to N-1) of signed(P downto 0);
29 type xy_vector is array(natural range <>) of signed(A-1 downto 0);
30 type z_vector is array(natural range <>) of signed(P downto 0);
31 constant init : signed(A-1 downto 0) := to_signed(integer(0.60725*2**(A-1)),A);
32
33 signal alpha : alpha_t;
34 signal x,y : xy_vector(N downto 0) := (others => (others => '0'));
35 signal z : z_vector(N downto 0) := (others => (others => '0'));
36 begin
37
38 table: for i in 0 to N-1 generate
39 alpha(i) <= to_signed(integer( atan(1.0/real(2**i)) / (2.0*math_pi) * real(2**P) ),P+1); -- math round to next integer
40 end generate;
41
42 process begin
43 wait until rising_edge(clk);
44 x(0) <= init;
45 y(0) <= (others => '0');
46 z(0) <= signed("000" & phi); -- 0..90° -> +- 0..360*
47 for i in 1 to N loop
48 if z(i-1) >= 0 then
49 x(i) <= x(i-1) - y(i-1) / 2**(i-1);
50 y(i) <= y(i-1) + x(i-1) / 2**(i-1);
51 z(i) <= z(i-1) - alpha(i-1);
52 else
53 x(i) <= x(i-1) + y(i-1) / 2**(i-1);
54 y(i) <= y(i-1) - x(i-1) / 2**(i-1);
55 z(i) <= z(i-1) + alpha(i-1);
56 end if;
57 end loop;
58 end process;
59
60 sin <= y(N);
61 cos <= x(N);
62
63 end behavioral;
64
This page was generated using GHDL 0.29 (20100109) [Sokcho edition], a program written by Tristan Gingold