1 -- title: LM4921 SPI Configuration
2 -- author: Sebastian Weiss
3 -- last change: 08.10.13
4
5 library IEEE;
6 use IEEE.std_logic_1164.all;
7 use IEEE.numeric_std.all;
8
9 entity lm4921_config is
10 port
11 (
12 clk : in std_logic;
13 rst : in std_logic;
14
15 mosi : out std_logic;
16 sclk : out std_logic;
17 cs : out std_logic;
18
19 init_done : out std_logic := '0'
20 );
21 end entity;
22
23 architecture behavioral of lm4921_config is
24 signal snd : std_logic_vector(15 downto 0) := (others => '0');
25 signal trigger : std_logic := '0';
26 signal rdy : std_logic;
27 signal init : std_logic := '0';
28 begin
29
30 spi : entity work.spi
31 generic map(
32 dlength => 16
33 )
34 port map(
35 clk => clk,
36 rcv => open,
37 snd => snd,
38 trigger => trigger,
39 mosi => mosi,
40 miso => '1',
41 sclk => sclk,
42 cs => cs,
43 rdy => rdy
44 );
45
46 process begin
47 wait until rising_edge(clk);
48 if rst = '1' then
49 init_done <= '0';
50 init <= '0';
51 else
52 if init = '0' then
53 snd <= b"0001_1110_1010_0111";
54 trigger <= '1';
55 init <= '1';
56 end if;
57 if init = '1' and rdy = '1' then
58 trigger <= '0';
59 init_done <= '1';
60 end if;
61 end if;
62 end process;
63
64 end behavioral;
65
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