1 -- title: SPI Master I/F
2 -- author: Stefan Biereigel
3 -- last change: 20.08.13
4
5 library ieee;
6 use ieee.std_logic_1164.all;
7 use ieee.numeric_std.all;
8
9 entity spi is
10 generic
11 (
12 dlength : integer := 8
13 );
14 port
15 (
16 clk : in std_logic;
17 snd : in std_logic_vector(dlength-1 downto 0);
18 rcv : out std_logic_vector(dlength-1 downto 0);
19 rdy : out std_logic := '1';
20 mosi : out std_logic := '1';
21 sclk : out std_logic := '1';
22 cs : out std_logic := '1';
23 miso : in std_logic;
24 trigger : in std_logic
25 );
26 end entity;
27
28 architecture rtl of spi is
29 type state_type is (idle, starttrx, outbit, inbit, endtrx);
30 signal state : state_type := idle;
31 signal outbuf : std_logic_vector(dlength-1 downto 0);
32 signal inbuf : std_logic_vector(dlength-1 downto 0);
33
34 begin
35 process
36 variable bitcnt : integer range 0 to dlength := 0;
37 begin
38 wait until rising_edge(clk);
39 -- state machine
40 case state is
41 when idle =>
42 inbuf <= (others => '0');
43 rdy <= '1';
44 cs <= '1';
45 if (trigger = '1') then
46 rdy <= '0';
47 outbuf <= snd;
48 state <= starttrx;
49 end if;
50 when starttrx =>
51 cs <= '0';
52 bitcnt := dlength;
53 state <= outbit;
54 when outbit =>
55 sclk <= '0';
56 mosi <= outbuf(0);
57 outbuf(dlength-1 downto 0) <= '0' & outbuf(dlength-1 downto 1); -- correct? verify
58 state <= inbit;
59 when inbit =>
60 sclk <= '1';
61 inbuf(0) <= miso;
62 inbuf(dlength-1 downto 1) <= inbuf(dlength-2 downto 0);
63 bitcnt := bitcnt - 1;
64 if (bitcnt = 0) then
65 state <= endtrx;
66 else
67 state <= outbit;
68 end if;
69 when endtrx =>
70 sclk <= '0';
71 mosi <= '0';
72 state <= idle;
73 rcv <= inbuf;
74 end case;
75 end process;
76 end rtl;
77
This page was generated using GHDL 0.29 (20100109) [Sokcho edition], a program written by Tristan Gingold