1 -- title: FT245 I/F
2 -- author: Sebastian Weiss
3 -- last change: 08.10.13
4
5
6 library IEEE;
7 use IEEE.std_logic_1164.all;
8 use IEEE.numeric_std.all;
9
10 entity ft245if is
11 port
12 (
13 clk : in std_logic;
14 rst : in std_logic;
15
16 usb_rd_n : out std_logic;
17 usb_wr : out std_logic;
18 usb_dq : inout std_logic_vector(7 downto 0);
19 usb_txe_n : in std_logic;
20 usb_rxf_n : in std_logic;
21
22 wr_d : in std_logic_vector(7 downto 0);
23 rd_d : out std_logic_vector(7 downto 0);
24 wr_req : in std_logic;
25 rd_req : in std_logic;
26 ready : out std_logic;
27 if_en : in std_logic
28 );
29 end entity;
30
31 architecture behavioral of ft245if is
32 -- signals for bus handling
33 signal wr_reg : std_logic_vector(7 downto 0);
34 signal rd_reg : std_logic_vector(7 downto 0) := (others => '0');
35 signal rd_n : std_logic := '1';
36 signal wr : std_logic := '0';
37 signal wr_en : std_logic;
38
39 -- signals for the controller
40 constant wr2wr_val : unsigned(2 downto 0) := "011";
41 constant wr_val : unsigned(2 downto 0) := "010";
42 constant rd2rd_val : unsigned(2 downto 0) := "101";
43 constant rd_val : unsigned(2 downto 0) := "011";
44 type state_t is (
45 idle,
46 wait_for_txe_low,
47 write_data,
48 wait_wr2wr,
49 wait_for_rxf_low,
50 read_data,
51 wait_rd2rd
52 );
53 signal state : state_t;
54 signal cnt : unsigned(2 downto 0);
55 begin
56
57 -- bus handling
58 usb_rd_n <= rd_n when if_en = '1' else 'Z';
59 usb_wr <= wr when if_en = '1' else 'Z';
60 wr_en <= rd_n and wr and if_en;
61 usb_dq <= wr_reg when wr_en = '1' else (others => 'Z');
62 rd_d <= rd_reg;
63
64 -- controller
65 process begin
66 wait until rising_edge(clk);
67 if (rst = '1') or (if_en = '0') then
68 state <= idle;
69 cnt <= "000";
70 end if;
71 case state is
72 when idle =>
73 ready <= '1';
74 if wr_req = '1' then
75 state <= wait_for_txe_low;
76 wr_reg <= wr_d;
77 end if;
78 if rd_req = '1' then
79 state <= wait_for_rxf_low;
80 end if;
81
82 when wait_for_txe_low =>
83 ready <= '0';
84 cnt <= "000";
85 wr <= '0';
86 if usb_txe_n = '0' then
87 state <= write_data;
88 end if;
89
90 when write_data =>
91 cnt <= cnt + "001";
92 wr <= '1';
93 if cnt >= wr_val then
94 state <= wait_wr2wr;
95 cnt <= "000";
96 end if;
97
98 when wait_wr2wr =>
99 cnt <= cnt + "001";
100 wr <= '0';
101 if cnt >= wr2wr_val then
102 if wr_req = '1' then
103 state <= wait_for_txe_low;
104 else
105 ready <= '1';
106 state <= idle;
107 end if;
108 end if;
109
110 when wait_for_rxf_low =>
111 ready <= '0';
112 cnt <= "000";
113 rd_n <= '1';
114 if usb_txe_n = '0' then
115 state <= read_data;
116 end if;
117
118 when read_data =>
119 cnt <= cnt + "001";
120 rd_n <= '0';
121 if cnt >= rd_val then
122 state <= wait_rd2rd;
123 cnt <= "000";
124 rd_reg <= usb_dq;
125 end if;
126
127 when wait_rd2rd =>
128 cnt <= cnt + "001";
129 rd_n <= '1';
130 if cnt >= rd2rd_val then
131 if rd_req = '1' then
132 state <= wait_for_rxf_low;
133 else
134 ready <= '1';
135 state <= idle;
136 end if;
137 end if;
138 end case;
139 end process;
140 end behavioral;
141
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