1 -- title: USB I/F
2 -- author: Sebastian Weiss
3 -- last change: 15.10.13
4
5 library IEEE;
6 use IEEE.std_logic_1164.all;
7 use IEEE.numeric_std.all;
8
9 entity usbif is
10 port
11 (
12 clk : in std_logic;
13 rst : in std_logic;
14 if_en : in std_logic;
15
16 usb_rd_n : out std_logic;
17 usb_wr : out std_logic;
18 usb_dq : inout std_logic_vector(7 downto 0);
19 usb_txe_n : in std_logic;
20 usb_rxf_n : in std_logic;
21
22 wr_req : in std_logic;
23 wr_full : out std_logic;
24 wr_data : in std_logic_vector(31 downto 0);
25 wr_clk : in std_logic;
26
27 rd_req : in std_logic;
28 rd_empty : out std_logic;
29 rd_data : out std_logic_vector(15 downto 0)
30 );
31 end entity;
32
33 architecture behavioral of usbif is
34 signal infifo_wrreq : std_logic;
35 signal infifo_full : std_logic;
36 signal infifo_data : std_logic_vector(15 downto 0);
37 signal outfifo_rdreq : std_logic;
38 signal outfifo_empty : std_logic;
39 signal outfifo_data : std_logic_vector(31 downto 0);
40 signal ft_rd_d : std_logic_vector(7 downto 0);
41 signal ft_rd_req : std_logic;
42 signal ft_incomming : std_logic;
43 signal ft_ready : std_logic;
44 signal ft_wr_d : std_logic_vector(7 downto 0);
45 signal ft_wr_req : std_logic;
46 begin
47
48 infifo : entity work.fifo16 port map(
49 clock => clk,
50 data => infifo_data,
51 rdreq => rd_req,
52 wrreq => infifo_wrreq,
53 empty => rd_empty,
54 full => infifo_full,
55 q => rd_data
56 );
57
58 outfifo : entity work.fifo32 port map(
59 data => wr_data,
60 rdclk => clk,
61 rdreq => outfifo_rdreq,
62 wrclk => wr_clk,
63 wrreq => wr_req,
64 q => outfifo_data,
65 rdempty => outfifo_empty,
66 wrfull => wr_full
67 );
68
69 ctrl : entity work.usbctrl port map(
70 clk => clk,
71 rst => rst,
72 infifo_wrreq => infifo_wrreq,
73 infifo_full => infifo_full,
74 infifo_data => infifo_data,
75 outfifo_rdreq => outfifo_rdreq,
76 outfifo_empty => outfifo_empty,
77 outfifo_data => outfifo_data,
78 rd_d => ft_rd_d,
79 rd_req => ft_rd_req,
80 incomming => ft_incomming,
81 ready => ft_ready,
82 wr_d => ft_wr_d,
83 wr_req => ft_wr_req
84 );
85
86 ft245 : entity work.ft245if port map(
87 clk => clk,
88 rst => rst,
89
90 usb_rd_n => usb_rd_n,
91 usb_wr => usb_wr,
92 usb_dq => usb_dq,
93 usb_txe_n => usb_txe_n,
94 usb_rxf_n => usb_rxf_n,
95
96 wr_d => ft_wr_d,
97 rd_d => ft_rd_d,
98 wr_req => ft_wr_req,
99 rd_req => ft_rd_req,
100 ready => ft_ready,
101 if_en => if_en
102 );
103
104 ft_incomming <= not usb_rxf_n;
105
106 end behavioral;
107
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